Lab-01

Introduction to simulation platform for Verilog HDL

In this lab we shall learn how to simulate a verilog code using online platform without using any installed software. Before starting, hope the readers are already aware of basic Verilog codes for digital system. We shall mention the code for a particular logic in next portions.

1) Step-1 skip if you are already aware of this)

Go to edaplayground (search it), and you will get a window as shown below. Check for log-in and login using your Google account.

Experiment: Design of 1 bit Full adder using data-flow modeling

//design code
module fa1(s,co,a,b,ci);
input a,b,ci;
output s,co;
//dataflow modeling
assign s=a^b^ci;
assign co=(a&b)|(b&ci)|(a&ci);
endmodule

//testbench code
module fa1_tb();
reg a,b,ci;
wire s,co;
fa1 U0 (s,co,a,b,ci);
initial begin
$dumpfile("dump.vcd");
$dumpvars;
a=0;b=0;ci=0;
#20;
a=0;b=0;ci=1;
#20;
a=0;b=1;ci=0;
#20;
a=0;b=1;ci=1;
#20;
a=1;b=0;ci=0;
#20;
a=1;b=0;ci=1;
#20;
a=1;b=1;ci=0;
#20;
a=1;b=1;ci=1;
#20;
$finish;
end
endmodule