Lab-05

Design of 1KB x 8 RAM and perform READ/WRITE operation

//RAM design
/code your verilog design here.
//1kb x 8
module ram(data,addr,we,clk,en,dout);
    input [7:0] data;
    input [9:0] addr;
    input we;
    input clk,en;
    output reg[7:0] dout;
   
   reg [7:0] ram[1023:0];
  
    always @(posedge clk) begin
    if(en)
        if(we)
        ram[addr]=data;
        else
        dout=ram[addr];
    else
        dout=8'bz;
    end
endmodule


//RAM testbench
//code your test bench here.
//remember to name the dump file as designname.vcd.
module ram_tb;
    reg we,clk,en;
    reg[7:0] data;
    reg[9:0] addr;
    wire[7:0] dout;
    ram DUT(data,addr,we,clk,en,dout);
    initial begin
    clk=0;
    en=1;
    we=1;
    #10;
    en=1;
    data=32;
    addr=10;
    #10;
        data=12;
        addr=20;
    #10;
    we=0;
    addr=10;
    #10;
    addr=20;
    #10 en=0;
    #20 en=1;
    $finish;
    end
    always #5 clk=~clk;
endmodule