Lab-06

Design of UP/DOWN synchronous counter using Behavioral modeling style

//design of up/down sync counter
module upcounter(count,rst,clk);
output reg [3:0] count;
input rst,clk;
initial count=0;
always @(posedge clk)
begin
if (rst)
count=0;
else
count=count+1;
end
endmodule


//testbench
//set runtime to 400ns
module counter_tb();
reg rst,clk;
wire [3:0] count;
upcounter L0(count,rst,clk);
initial begin
  $dumpfile("dump.vcd");
  $dumpvars;
clk=0;rst=1;
#20;
rst=0;
#400;
$finish;
end
always #10 clk=~clk;
endmodule

*Note: Same program can be converted to down counter with count=count-1.

*In updown counter there is a extra pin called updown. Depending upon status of this pin the counter will count either in up or in down direction.

//up-down counter
// Code your design here
module upcounter(count,rst,clk,updown);
output reg [3:0] count;
input rst,clk,updown;
initial count=0;
always @(posedge clk)
begin
if (rst)
count=0;
else
  if(updown)
count=count+1;
  else
    count=count-1;
end
endmodule

//testbench
module counter_tb();
reg rst,clk,updown;
wire [3:0] count;
  upcounter L0(count,rst,clk,updown);
initial begin
  $dumpfile("dump.vcd");
  $dumpvars;
clk=0;rst=1;updown=0;
#20;
rst=0;
  #100;
  updown=1;
  #200;
  updown=0;
  #400;
  $finish;
end
always #10 clk=~clk;
endmodule