Lab-07

Design of 4-bit asynchronous counter (Up and down both)

*Note: You can use the same testbench which was used in Lab-6.

// Code your design here
//upcounter
module async(count,rst,clk);
output reg [3:0] count;
input rst,clk;
initial count=0;
  
always @(posedge clk)
begin
  if(rst)
        count=0;
  else
  count[0]=~count[0];
end
 
  always @(posedge ~count[0])
begin
  if(rst)
        count=0;
  else
  count[1]=~count[1];
end
 
  always @(posedge ~count[1])
begin
  if(rst)
        count=0;
  else
  count[2]=~count[2];
end
 
  always @(posedge ~count[2])
begin
  if(rst)
        count=0;
  else
  count[3]=~count[3];
end
 
endmodule

//downcounter
// Code your design here
module async(count,rst,clk);
output reg [3:0] count;
input rst,clk;
initial count=0;
  
always @(posedge clk)
begin
  if(rst)
        count=0;
  else
  count[0]=~count[0];
end
 
  always @(posedge count[0])
begin
  if(rst)
        count=0;
  else
  count[1]=~count[1];
end
 
  always @(posedge count[1])
begin
  if(rst)
        count=0;
  else
  count[2]=~count[2];
end
 
  always @(posedge count[2])
begin
  if(rst)
        count=0;
  else
  count[3]=~count[3];
end
 
endmodule