Lab-08

Design of 101 non-overlapping sequence detector using Moore FSM

// Code your design here
module moore101nov(dout,din,rst,clk);
  input rst,clk,din;
  output reg dout;
  reg [1:0] state;
  parameter s0=0,s1=1,s2=2,s3=3;
  initial dout=0;
  initial state=0;
  always @(posedge clk)
    begin
      if(rst)
        begin
          state=0;
          dout=0
        end
      else
        case(state)
          s0: begin
            if(din)
              state=s1;
            else
              state=s0;
             end
          s1: begin
            if(din)
              state=s1;
            else
              state=s2;
             end
        s2: begin
            if(din)
              state=s3;
            else
              state=s0;
             end
         s3: state=s0;
        endcase
    end
always @(state) begin
    case(state)
      s0: dout=0;
      s1: dout=0;
      s2: dout=0;
      s3: dout=1;
    endcase
  end
endmodule

//testbench
// Code your testbench here
// or browse Examples
module moore101_tb();
  reg din,clk,rst;
  wire dout;
  moore101nov L00(dout,din,rst,clk);
  initial begin
    $dumpfile("dump.vcd");
    $dumpvars;
    clk=0;
    rst=1;
    din=0;
    #10;
    rst=0;
    din=0;#10;
    din=1;#10;
    din=0;#10;
    din=1;#10;
    din=0;#10;
    din=0;#10;
    din=1;#10;
    din=0;#10;
    din=1;#10;
    din=0;#10;
    din=1;#10;
    din=0;#10;
    din=0;#100;
    $finish;   
  end
  always #5 clk=!clk;
endmodule