Gate Array Based Design: 

In this design style, the transistors are predefined on a silicon wafer. These are called a base array or base cell. Only the top few layers of metal which are used to make interconnections are customized. The designer chooses a pre-verified gate array library of logic cells. These are termed as "macros". The designer needs to define the interconnections between the base array.  Depending upon the configuration of base cells, there are three different types of gate array-based design, (1) channel-less (2) Channelled, and (3) Structured gate array.

(1) Channel-less gate array: 

• Only some of the mask layers are customized.
• Manufacturing lead time between two days to two weeks

(2) Channelled gate array: 

• Only interconnect is customized.
• Interconnect uses pre-defined spaces between row and base cell.
• Manufacturing time is the same as a channel-less gate array.

(3) Structured gate array:

• Only interconnect is customized.
• Custom blocks can be embedded by the designer.
• Manufacturing time is almost the same as other types of gate array-based design.

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